1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device preferable for formation of a wire layer.
2. Description of the Related Art
Following a demand for large-scale high integration and enhancement of speed of a semiconductor integrated circuit, a multilayered wire material with a low resistance and an interlayer insulating material of a small capacity are required. Consequently, in recent years, in order to meet the aforesaid demand, copper (Cu) comes to be used as a wire material and a low dielectic material comes to be used as an interlayer insulating film material, though an aluminum (Al) alloy has been used as a multilayered wire material and a silicone (SiO) oxide has been used as an interlayer insulating film material before.
However, microprocessing of copper itself is very difficult, and therefore a Damascene method is mainly employed to form a copper wire. The Damascene method is the method for forming a wire by forming a trench pattern, a via hole pattern and the like in an insulating film, thereafter, burying a copper material into these patterns, and then polishing (CMP: Chemical Mechanical Polishing) the copper material. In the Damascene method, there are a Dual Damascene method for forming a trench and a hole at the same time, and a Single Damascene method for forming them independently.
In many semiconductor devices, a plurality of wire layers are formed, and in their manufacturing process, a step of forming a via hole on a copper wire is required. However, copper has lower durability against oxygen plasma as compared with an aluminum alloy, which has been used as a wire material before. For this reason, when a resist mask used for formation of a via hole is removed, if the same ashing condition as in the case of the aluminum alloy is used as it is, there is a high possibility that a problem such as imperfect contact will occur. Consequently, in order to avoid such a problem, a processing method in which a surface of a copper wire is not exposed at the time of ashing is established.
In this processing method, a diffusion preventing film is formed between the copper wire and an interlayer insulating film, so that the diffusion preventing film temporarily stops formation of a trench pattern or a via hole pattern into the interlayer insulating film. Then, a resist mask is removed by ashing, and thereafter, the diffusion preventing film is etched. According to such a method, the surface of the copper wire is hardly exposed to oxygen plasma, and therefore the problem such as imperfect contact is prevented.
However, at least the surface of the copper wire is exposed at the time of etching of the diffusion preventing film. For this reason, it is known that at this time (when the surface of the copper wire is exposed), a reaction product adheres to a side wall portion and the like of the trench pattern. Consequently, wet treatment using a chemical solution is conventionally performed after etching of the diffusion preventing film, which is the last dry etching, is performed, and thereby the reaction product is removed.
Prior arts are disclosed in Japanese Patent Laid-open No. 11-312669, and Japanese Patent Laid-open No. 2001-284327.
However, in the case in which an SiO2 film is used as the interlayer insulating film, a problem does not especially occur in the aforementioned conventional method, but when an SiOC film comes to be used recently as the interlayer insulating film with a lower dielectric constant, contact resistance rises, yields are reduced, and reliability is reduced.
The present invention is made in view of the above problems, and has its object to provide a manufacturing method of a semiconductor device capable of suppressing rise in contact resistance, reduction in yields and reliability even when the SiOC film is used as the interlayer insulating film.